1. Field of the Invention
The present invention generally relates to current switching circuits employing an inverter constituted by a p-channel MOS transistor and an n-channel MOS transistor in a Si-CMOS integrated circuit (IC) or a pnp bipolar transistor and an npn bipolar transistor in a Si-bipolar junction transistor (BJT IC), for example, a current switching circuit for switching output data, which is used for a current mode logic (CML) mode selector circuit and, more particularly, to a current switching circuit in which even if a supply voltage larger than a breakdown voltage of constituent transistors is used, it is guaranteed that voltages applied to the transistors do not exceed the breakdown voltage.
2. Description of the Prior Art
On account of remarkable progress of miniaturization of Si-CMOS processing and Si-BJT processing in recent years, Si-CMOS and Si-BJT ICs have high-speed response characteristics equivalent to or better than those of GaAs devices. Thus, the Si-CMOS and the Si-BJT ICs have rapidly expanded their fields of application to optical communication ICs and radio communication ICs, operating at frequencies exceeding several GHz and act as key devices for lowering production cost of each system.
High-speed performance obtained by miniaturization of transistors brings about drop of a device breakdown voltage. It has so far been a general practice that in order to secure reliability of a circuit, a regulator or the like reduces a supply voltage of the circuit lower than a device breakdown voltage from a supply voltage specified for each system. However, in case an output amplitude approximate to the breakdown voltage is necessary in a circuit in which a switching transistor and a current source transistor are vertically stacked on each other as in a differential circuit, the supply voltage of the circuit should be set higher than the device breakdown voltage. If the differential circuit and a current switching circuit are used in combination under these circumstances, a problem arises that a voltage not less than the breakdown voltage is surely applied to one of a p-channel MOS transistor or a pnp bipolar transistor and an n-channel MOS transistor or an npn bipolar transistor, thereby resulting in device breakdown.
FIG. 17 shows one example of a configuration of a conventional current switching circuit employing a CMOS IC. The conventional current switching circuit of FIG. 17 includes a positive power source 1 having a positive voltage Vdd, a negative power source 2 having a negative voltage Vss, a signal input terminal IN, signal output terminals OUT1 and OUT2, n-channel MOS transistors Q1, Q2 and Q10 for supplying an output current to the signal output terminal OUT1 and a resistance element 11 having a resistance R1. The resistance element 11 determines a drain current flowing through the n-channel MOS transistor Q2. The conventional current switching circuit further includes a p-channel MOS transistor Q3, an n-channel MOS transistor Q4, n-channel MOS transistors Q5 and Q13 for supplying an output current to the signal output terminal OUT2 and a resistance element 12 having a resistance R2. A CMOS inverter 20 is constituted by the p-channel MOS transistor Q3 and the n-channel MOS transistor Q4. The resistance element 12 determines a drain current flowing through the n-channel MOS transistor Q5.
In the conventional current switching circuit of FIG. 17, it is supposed, for example, that the positive power source 1 is grounded and the negative voltage Vss supplied to the negative power source 2 satisfies a relation of (|Vss| greater than 2xc3x97Vth) where Vth is, for example, a positive threshold voltage of the transistors Q1 to Q5. Initially, a case is considered in which the signal input terminal IN is at high level upon reception of, for example, the positive voltage Vdd. In this case, since a gate-source voltage Vgs1 of the transistor Q1 and a gate-source voltage Vgs2 of the transistor Q2 become larger than the threshold voltage Vth, the transistors Q1 and Q2 are turned on and thus, a drain current Id2 flows through both of the transistors Q1 and Q2. The drain current Id2 is determined by the resistance R1 of the resistance element 11 and a voltage across opposite ends of the resistance element 11.
Since a gate voltage Vg2 (xe2x89xa0Vss) generated in the transistor Q2 in response to the drain current Id2 is applied to a gate terminal of the transistor Q10, a drain current Id10 flows through the transistor Q10 in response to a gate-source voltage of the transistor Q10. If a drain voltage of the transistor Q11 is biased in a saturation area, the drain current Id10 is substantially determined by a ratio of a gate width Wq2 of the transistor Q2 to a gate width Wq10 of the transistor Q10, i.e., (Wq2/Wq10) and a relation of {Id10=Id2xc3x97(Wq10/Wq2)} is obtained. The drain current Id10 flows to the signal output terminal OUT1.
The signal input terminal IN is also connected to gate terminals of the p-channel MOS transistor Q3 and the n-channel MOS transistor Q4. Since the signal input terminal IN has the positive voltage Vdd, a gate-source voltage Vgs3 of the p-channel MOS transistor Q3 is smaller than the threshold voltage Vth, so that the p-channel MOS transistor Q3 is turned off. On the other hand, since a gate-source voltage Vgs4 of the n-channel MOS transistor Q4 becomes larger than the threshold voltage Vth, the n-channel MOS transistor Q4 is turned on and a drain voltage of the n-channel MOS transistor Q4 drops to the negative voltage Vss.
Thus, since an output from the CMOS inverter 20, namely, a junction of a drain terminal of the p-channel MOS transistor Q3 and a drain terminal of the n-channel MOS transistor Q4 has the negative voltage Vss, electric current does not flow through the resistance element 12 and the transistor Q5, so that a gate voltage Vg5 of the transistor Q5 also has the negative voltage Vss. Since this gate voltage Vg5 (=Vss) of the transistor Q5 is applied to a gate terminal of the transistor Q13, a gate-source voltage Vgs13 of the transistor Q13 becomes smaller than the threshold voltage Vth and thus, a drain current does not flow through the transistor Q13. Therefore, there is no electric current flowing to a drain terminal of the transistor Q13 from the signal output terminal OUT2.
Then, a case is considered in which the signal input terminal IN is at law level upon reception of, for example, the negative voltage Vss. In this case, since electric current does not flow through the transistors Q1 and Q2 and the resistance element 11, there is no electric current flowing from the signal output terminal OUT1. Since the signal input terminal IN has the negative voltage Vss, the gate-source voltage Vgs3 of the p-channel MOS transistor Q3 becomes larger than the threshold voltage Vth and thus, the channel MOS transistor Q3 is turned on. On the other hand, since the gate-source voltage Vgs4 of the n-channel MOS transistor Q4 becomes smaller than the threshold voltage Vth, the n-channel MOS transistor Q4 is turned off and the drain voltage of the n-channel MOS transistor Q4 rises to the positive voltage Vdd. Therefore, an output from the CMOS inverter 20 has the positive voltage Vdd.
Hence, a voltage is applied across opposite ends of the resistance element 12 and thus, a drain current Id5 flows through the transistor Q5. The drain current Id5 is determined by the resistance R2 of the resistance element 12 and a voltage across opposite ends of the resistance element 12. Since the gate voltage Vg5 generated in the transistor Q5 in response to the drain current Id5 is applied to the gate terminal of the transistor Q13, a drain current Id13 generated in response to the gate-source voltage Vgs13 (=Vg5xe2x88x92Vss) of the transistor Q13 flows from the signal output terminal OUT2.
Even if the signal output terminal is switched to either one of OUT1 and OUT2 in response to an input signal by setting the resistance R1 of the resistance element 11 and the resistance R2 of the resistance element 12 such that a relation of (Id2=Id5) is satisfied, a substantially identical quantity of electric current flows into a selected one of the signal output terminals OUT1 and OUT2. Therefore, since the current switching circuit is capable of switching for causing an electric current to flow through either one of the transistors Q2 and Q5 by setting an input voltage at high level or low level, the signal output terminal for outputting electric current can be switched to either of OUT1 and OUT2.
FIG. 18 shows one example of a selector circuit to which the conventional current switching circuit of FIG. 17 is applied. In FIG. 18, a rectangular portion enclosed by broken lines represents the conventional current switching circuit of FIG. 17. The known selector circuit of FIG. 18 includes n-channel MOS transistors Q8 and Q9 which have source terminals connected to each other so as to form a differential pair. A drain terminal of the n-channel MOS transistor Q10 is connected to a junction of the source terminals of the differential pair of the n-channel MOS transistors Q8 and Q9 such that the n-channel MOS transistor Q10 acts as a current source transistor for determining, in accordance with a voltage inputted to the gate terminal of the n-channel MOS transistor Q10, electric current flowing through the differential pair. The gate voltage of the n-channel MOS transistor Q10 is supplied from a gate terminal of the n-channel MOS transistor Q2.
The known selector circuit further includes n-channel MOS transistors Q11 and Q12 which have source terminals connected to each other so as to form a differential pair. A drain terminal of the n-channel MOS transistor Q13 is connected to a junction of the source terminals of the differential pair of the n-channel MOS transistors Q11 and Q12 such that the n-channel MOS transistor Q13 acts as a current source transistor for determining, in accordance with a voltage inputted to the gate terminal of the n-channel MOS transistor Q13, electric current flowing through the differential pair. The gate voltage of the n-channel MOS transistor Q13 is supplied from a gate terminal of the n-channel MOS transistor Q5. The known selector circuit further includes a resistance element 18 having a load resistance R8 and a resistance element 19 having a load resistance R9. The resistance element 18 is connected between drain terminals of the transistors Q8 and Q11 and the positive power source 1, while the resistance element 19 is connected between drain terminals of the transistors Q9 and Q12 and the positive power source 1.
Meanwhile, the known selector circuit further includes a data input terminal DA1 for the selector circuit, a data input terminal DA2 complementary to the data input terminal DA1, a further data input terminal DA3, a data input terminal DA4 complementary to the data input terminal DA3, a signal output terminal O1 for the selector circuit and a signal output terminal O2 complementary to the signal output terminal O1.
In case the signal input terminal IN is at high level upon reception of, for example, the positive voltage Vdd, the gate voltage Vg2 (xe2x89xa0Vss) of the transistor Q2 is applied to the gate terminal of the transistor Q10 and thus, the drain current Id10 flows through the transistor Q10 in response to the gate-source voltage of the transistor Q10. If the drain voltage of the transistor Q10 is biased in the saturation area, the drain current Id10 is substantially determined by the ratio of the gate width Wq2 of the transistor Q2 to the gate width Wq10 of the transistor Q10, i.e., (Wq2/Wq10) and a relation of {Id10=Id2xc3x97(Wq10/Wq2)} is obtained. The drain current Id10 is switched to either one of the transistors Q8 and Q9 in response to complementary signal voltages inputted to the data input terminals DA1 and DA2, respectively and flows through the resistance element 18 or 19 connected to the drain terminal of the transistor Q8 or Q9. As a result, a voltage signal having a voltage equal to (R8xc3x97Id10) or (R9xc3x97Id10) is outputted to the signal output terminal O1 or O2.
On the other hand, since the gate voltage Vg5 (=Vss) of the transistor Q5 is applied to the gate terminal of the transistor Q13, a gate-source voltage Vg13 of the transistor Q13 becomes smaller than the threshold voltage Vth, so that no drain current flows through the transistor Q13. Therefore, even if any signal is inputted to each of the data input terminals DA3 and DA4, no electric current flows through the resistance elements 18 and 19 via the transistors Q11 and Q12, so that the signals inputted to the data input terminals DA3 and DA4 do not exert any influence on signals fetched from the signal output terminals O1 and O2.
On the contrary, in case the signal input terminal IN is at low level upon reception of, for example, the negative voltage Vss, the gate voltage of the transistor Q10 assumes Vss and a gate voltage of the transistor Q13 assumes Vg3 (xe2x89xa0Vss), so that electric current flows through the transistor Q13 and thus, the signals fetched from the signal output terminals O1 and O2 depend on only the signals inputted to the data input terminals DA3 and DA4 and are not affected at all by signals inputted to the data input terminals DA1 and DA2. Thus, by setting the input voltage of the current switching circuit at high level or low level in the known selector circuit of FIG. 18, it is possible to switch electric current to flow through either one of the transistors Q10 and Q13, so that it is possible to select whether the input signals of the data input terminals DA1 and DA2 are used or the input signals of the data input terminals DA3 and DA4 are used.
In view of reliability of the known selector circuit of FIG. 18, it has been a general practice to set a supply voltage (=Vddxe2x88x92Vss) at not more than a device breakdown voltage. It is assumed here that a drain-source breakdown voltage BVds, a gate-drain breakdown voltage BVgd and a gate-source breakdown voltage BVgs are substantially equal to one another. For example, in the case of a MOS transistor having a gate length of 2.5 xcexcm, the device breakdown voltage is 2.5 V and thus, the supply voltage is set at not more than 2.5 V. Meanwhile, in the case of a MOS transistor having a gate length of 1.8 xcexcm, the device breakdown voltage is 1.8 V and thus, the supply voltage is set at not more than 1.8 V.
In order to improve high-speed response characteristics of circuits, progress in high-speed response of devices has so far been made by miniaturization at the sacrifice of the device breakdown voltage. On the other hand, a predetermined level is required of output amplitudes of the circuits irrespective of the device breakdown voltage. In order to meet the recent demand for higher-speed response of the devices, the device breakdown voltage is required to be lowered to a level equivalent to that of the output amplitudes.
If an output amplitude which is so large as to be equivalent to the device breakdown voltage is obtained from the signal output terminals Q1 and Q2 in the known selector circuit of FIG. 18, a bias voltage approximate to the device breakdown voltage should be applied between a drain and a source of each of the transistors Q8, Q9, Q11 and Q12. In this case, the supply voltage (=Vddxe2x88x92Vss) should be set at a sum of the device breakdown voltage and a drain-source voltage of the transistors Q10 and Q13, which drain-source voltage is a voltage required for operation in a saturation area.
At this time, the breakdown voltage of the p-channel MOS transistor Q3 and the n-channel MOS transistor Q4 in the CMOS inverter 20 of the current switching circuit poses a problem. In case the signal input terminal IN is at high level upon reception of, for example, the positive voltage Vdd, a drain voltage of the transistors Q3 and Q4 assumes Vss, so that a bias not less than the device breakdown voltage is applied between a drain terminal and a source terminal and between a gate terminal and the drain terminal of the transistor Q3 as well as between a gate terminal and a source terminal and between the gate terminal and a drain terminal of the transistor Q4, thereby resulting in such an inconvenience as device breakdown.
In case the signal input terminal IN is at low level upon reception of, for example, the negative voltage Vss, the drain voltage of the transistors Q3 and Q4 assumes Vdd, so that a bias not less than the device breakdown voltage is applied between the gate terminal and the source terminal and between the gate terminal and the drain terminal of the transistor Q3 as well as between the drain terminal and the source terminal and between the gate terminal and the drain terminal of the transistor Q4, thus resulting in also such a disadvantage as device breakdown.
Accordingly, an essential object of the present invention is to provide, with a view to eliminating the above mentioned drawbacks of prior art, a current switching circuit in which even if a supply voltage larger than a breakdown voltage of respective devices is used, it is guaranteed that voltages applied to the devices do not exceed the breakdown voltage.
In order to accomplish this object of the present invention, a current switching circuit according to the present invention includes a complementary circuit which is connected between a first power source and a second power source having a potential lower than that of the first power source. One of a pair of current mirror circuits is connected to the complementary circuit. A level shift element is connected between one of the first and second power sources and the complementary circuit and imparts a predetermined voltage drop to the complementary circuit by a level shift current flowing through the level shift element. In response to an input signal of a first level, the complementary circuit switches one of the current mirror circuits to a first state in which that current mirror circuit is enabled, by supplying a first current mirror current thereto and the other of the current mirror circuits is disabled, and in response to an input signal of a second level switches the one of the current mirror circuits to a second state in which the one of the current mirror circuits is disabled and the other of the current mirror circuits is enabled and a second current mirror current is supplied thereto. At least one of the first and second current mirror currents flows through the level shift circuit as a level shift current.